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caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd. hcpl-316j 2.5 amp gate drive optocoupler with integrated (v ce ) desaturation detection and fault status feedback data sheet description avagos 2.5 amp gate drive optocoupler with integrated desaturation (v ce ) detection and fault status feedback makes igbt v ce fault protection compact, affordable, and easy-to-implement while satisfying worldwide safety and regulatory requirements. features 2.5 a maximum peak output current drive igbts up to i c = 150 a, v ce = 1200v optically isolated, fault status feedback so-16 package cmos/ttl compatible 500 ns max. switching speeds fault protected igbt gate drive micro-controller m hcpl - 316j Chv +hv isolation boundary hcpl - 316j isolation boundary hcpl - 316j isolation boundary hcpl - 316j isolation boundary hcpl - 316j isolation boundary hcpl - 316j isolation boundary hcpl - 316j isolation boundary 3-phase input fault features (continued) soft igbt turn-off integrated fail-safe igbt protection C desat (v ce ) detection C under voltage lock-out protection (uvlo) with hysteresis user configurable: inverting, noninverting, auto-reset, auto-shutdown wide operating v cc range: 15 to 30 volts -40c to +100c operating temperature range 15 kv/s min. common mode rejection (cmr) at v cm = 1500v regulatory approvals: ul, csa, iec/en/din en 60747- 5-2 (1230v peak working voltage) lead (pb) free rohs 6 fully compliant r o h s 6 f u lly comp l iant options avai l ab l e ; -xxxe denotes a l ead -f ree product
2 desat condition pin 6 uvlo detected on (fault) v in+ v in- (v cc2 - v e ) pin 14 output v out x x active x x low x x x yes low low low x x x x low x high x x x low high low not active no high high typical fault protected igbt gate drive circuit the hcpl-316j is an easy-to-use, intelligent gate driver which makes igbt v ce fault protection compact, afford- able, and easy-to-implement. features such as user con- figurable inputs, integrated v ce detection, under volt- figure 1. typical desaturation protected gate drive circuit, noninverting. output control the outputs (v out and fault) of the hcpl-316j are con- trolled by the combination of v in , uvlo and a detected igbt desat condition. as indicated in the below table, the hcpl-316j can be configured as inverting or non-invert- ing using the v in+ or v in- inputs respectively. when an in- verting configuration is desired, v in+ must be held high and v in- toggled. when a non-inverting configuration is desired, v in- must be held low and v in+ toggled. once uvlo is not active (v cc2 - v e > v uvlo ), v out is allowed to go high, and the desat (pin 14) detection feature of the hcpl-316j will be the primary source of igbt protection. uvlo is needed to ensure desat is functional. once v u- vlo+ > 11.6 v, desat will remain functional until v uvlo- < 12.4 v. thus, the desat detection and uvlo features of the hcpl-316j work in conjunction to ensure constant igbt protection. * these components are only required when negative gate drive is implemented. description of operation during fault condition 1. desat terminal monitors the igbt v ce voltage through d desat . 2. when the voltage on the desat terminal exceeds 7 volts, the igbt gate voltage (v out ) is slowly lowered. 3. fault output goes low, notifying the microcontroller of the fault condition. 4. microcontroller takes appropriate action. + C + C * * * c blank d desat r pull-down 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 v e v led2+ desat v cc2 v c v out v ee v ee v in+ v in- v cc1 gnd1 reset fault v led1+ v led1- hcpl-316j + C c r f v f +C r g v ce v ce + C + C 100 age lockout (uvlo), soft igbt turn-off and isolated fault feed back provide maximum design flexibility and circuit protection.
3 product overview description the hcpl-316j is a highly integrated power control de- vice that incorporates all the necessary components for a complete, isolated igbt gate drive circuit with fault pro- tection and feedback into one so-16 package. ttl input logic levels allow direct interface with a microcontroller, and an optically isolated power output stage drives igbts with power ratings of up to 150 a and 1200 v. a high speed internal optical link minimizes the propaga- tion delays between the microcontroller and the igbt while allowing the two systems to operate at very large common mode voltage differences that are common in industrial motor drives and other power switching ap- plications. an output ic provides local protection for the igbt to prevent damage during overcurrents, and a second optical link provides a fully isolated fault status feedback signal for the microcontroller. a built in watch- dog circuit monitors the power stage supply voltage to prevent igbt caused by insufficient gate drive voltages. this integrated igbt gate driver is designed to increase the performance and reliability of a motor drive without the cost, size, and complexity of a discrete design. two light emitting diodes and two integrated circuits housed in the same so-16 package provide the input control circuitry, the output power stage, and two op- tical channels. the input buffer ic is designed on a bi- polar process, while the output detector ic is designed manufactured on a high voltage bicmos/power dmos process. the forward optical signal path, as indicated by led1, transmits the gate control signal. the return opti- cal signal path, as indicated by led2, transmits the fault status feedback signal. both optical channels are com- pletely controlled by the input and output ics respec- tive-ly, making the internal isolation boundary transpar- ent to the microcontroller. under normal operation, the input gate control signal di- rectly controls the igbt gate through the isolated output detector ic. led2 remains off and a fault latch in the in- put buffer ic is disabled. when an igbt fault is detected, the output detector ic immediately begins a soft shut- down sequence, reducing the igbt current to zero in a controlled manner to avoid potential igbt damage from inductive overvoltages. simultaneously, this fault status is transmitted back to the input buffer ic via led2, where the fault latch disables the gate control input and the ac- tive low fault output alerts the microcontroller. during power-up, the under voltage lockout (uvlo) fea- ture prevents the application of insufficient gate voltage to the igbt, by forcing the hcpl-316js output low. once the output is in the high state, the desat (v ce ) detec- tion feature of the hcpl-316j provides igbt protection. thus, uvlo and desat work in conjunction to provide constant igbt protection. shield desat fault uvlo output ic shield input ic reset 5 fault 6 v in+ 1 v in- 2 v cc1 3 v cc2 13 12 v out 11 v ee 9,10 v e 16 desat 14 v c v led2+ gnd1 15 4 v led1- 7 8 v led1+ led2 led1 d r i v e r
4 package pin out 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 v e v led2+ desat v cc2 v c v out v ee v ee v in+ v in- v cc1 gnd1 reset fault v led1+ v led1- pin descriptions symbol description symbol description v in+ noninverting gate drive voltage output (v out ) v e common (igbt emitter) output supply voltage. control input. v in- inverting gate drive voltage output v led2+ led 2 anode. this pin must be left unconnected (v out ) control input. for guaranteed data sheet performance. (for optical coupling testing only.) v cc1 positive input supply voltage. (4.5 v to 5.5 v) desat desaturation voltage input. when the voltage on desat exceeds an internal reference voltage of 7 v while the igbt is on, fault output is changed from a high impedance state to a logic low state within 5 s. see note 25. gnd1 input ground. v cc2 positive output supply voltage. reset fault reset input. a logic low input for at least v c collector of output pull-up triple-darlington 0.1 s, asynchronously resets fault output high transistor. it is connected to v cc2 directly or and enables v in . synchronous control of reset through a resistor to limit output turn-on relative to v in is required. reset is not affected current. by uvlo. asserting reset while v out is high does not affect v out . fault fault output. fault changes from a high v out gate drive voltage output. impedance state to a logic low output within 5 s of the voltage on the desat pin exceeding an internal reference voltage of 7 v. fault output remains low until reset is brought low. fault output is an open collector which allows the fault outputs from all hcpl-316js in a circuit to be connected together in a wired or forming a single fault bus for interfacing directly to the micro-controller. v led1+ led 1 anode. this pin must be left unconnected v ee output supply voltage. for guaranteed data sheet performance. (for optical coupling testing only.) v led1- led 1 cathode. this pin must be connected to ground.
5 package outline drawings 16-lead surface mount dimensions in inches (millimeters) notes: initial and continued variation in the color of the hcpl-316js white mold compound is normal and does note affect device performance or reliability. floating lead protrusion is 0.25 mm (10 mils) max. ordering information hcpl-316j is ul recognized with 5000 vrms for 1 minute per ul1577. part number option package surface mount tape & reel iec/en/din en 60747-5-2 quantity rohs compliant non rohs compliant hcpl-316j -000e no option so-16 x x 45 per tube -500e #500 x x x 850 per reel to order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. example 1: hcpl-316j-500e to order product of so-16 surface mount package in tape and reel packaging with iec/en/din en 60747-5-2 safety approval in rohs compliant. example 2: hcpl-316j to order product of so-16 surface mount package in tube packaging with iec/en/din en 60747-5-2 safety approval and non rohs compliant. option datasheets are available. contact your avago sales representative or authorized distributor for information. remarks: the notation #xxx is used for existing products, while (new) products launched since 15th july 2001 and rohs compliant option will use -xxxe. 9 0.295 0.010 (7.493 0.254) 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1 0.018 (0.457) 0.138 0.005 (3.505 0.127) 9 0.406 0.10 (10.312 0.254) 0.408 0.010 (10.363 0.254) 0.025 min. 0.008 0.003 (0.203 0.076) standoff 0.345 0.010 (8.763 0.254) 0C8 0.018 (0.457) 0.050 (1.270) all leads to be coplanar 0.002 a 316j yyww type number date code 0.458 (11.63) 0.085 (2.16) 0.025 (0.64) land pattern recommendation
6 recommended pb-free ir profile recommended reflow condition as per jedec standard, j-std-020 (latest revision). non-halide flux should be used. package characteristics all specifications and figures are at the nominal (typical) operating conditions of v cc1 = 5 v, v cc2 - v ee = 30 v, v e - v ee = 0 v, and t a = +25c. parameter symbol min. typ. max. units test conditions note input-output momentary v iso 5000 v rms rh < 50%, t = 1 min., 1, 2, withstand voltage t a = 25c 3 resistance (input-output) r i-o >10 9 v i-o = 500 vdc 3 capacitance (input-output) c i-o 1.3 pf f = 1 mhz output ic-to-pins 9 &10 o9-10 30 c/w t a = 100c thermal resistance input ic-to-pin 4 thermal resistance i4 60
7 regulatory information the hcpl-316j has been approved by the following organizations: figure 2. dependence of safety limiting values on temperature. p s C power C mw 0 0 t s C case temperature C c 200 1200 800 25 1400 50 75 100 400 150 175 p s , output p s , input 125 200 600 1000 ul recognized under ul 1577, component recognition program, file e55361. csa approved under csa component acceptance notice #5, file ca 88324. iec/en/din en 60747-5-2 insulation characteristics* description symbol characteristic unit installation classification per din vde 0110/1.89, table 1 for rated mains voltage 150 vrms i - iv for rated mains voltage 300 vrms i - iv for rated mains voltage 600 vrms i - iv for rated mains voltage 1000vrms i - iii climatic classification 55/100/21 pollution degree (din vde 0110/1.89) 2 maximum working insulation voltage v iorm 1230 v peak input to output test voltage, method b** v iorm x 1.875 = v pr , 100% production test with t m = 1 sec, v pr 2306 v peak partial discharge < 5 pc input to output test voltage, method a** v iorm x 1.6 = v pr , type and sample test, t m = 10 sec, v pr 1968 v peak partial discharge < 5 pc highest allowable overvoltage** (transient overvoltage t ini = 60 sec) v iotm 8000 v peak safety-limiting values C maximum values allowed in the event of a failure, also see figure 2. case temperature t s 175 c input power p s, input 400 mw output power p s, output 1200 mw insulation resistance at t s , v io = 500 v r s >10 9 * isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application. surface mount classification is class a in accordance with ceccoo802. **refer to the optocoupler section of the isolation and control components designers catalog, under product safety regulations section iec/ en/din en 60747-5-2, for a detailed description of method a and method b partial discharge test profiles. iec/en/din en 60747-5-2 approved under: iec 60747-5-5:1997 + a1:2002 en 60747-5-2:2001 + a1:2002 din en 60747-5-2 (vde 0884 teil 2):2003-01.
8 insulation and safety related specifications parameter symbol value units conditions minimum external air gap l(101) 8.3 mm measured from input terminals to output terminals, (clearance) shortest distance through air. minimum external tracking l(102) 8.3 mm measured from input terminals to output terminals, (creepage) shortest distance path along body. minimum internal plastic gap 0.5 mm through insulation distance conductor to (internal clearance) conductor, usually the straight line distance thickness between the emitter and detector. tracking resistance cti >175 volts din iec 112/vde 0303 part 1 (comparative tracking index) isolation group iiia material group (din vde 0110, 1/89, table 1) absolute maximum ratings parameter symbol min. max. units note storage temperature t s -55 125 c operating temperature t a -40 100 output ic junction temperature t j 125 4 peak output current |i o(peak) | 2.5 a 5 fault output current i fault 8.0 ma positive input supply voltage v cc1 -0.5 5.5 volts input pin voltages v in+ , v in- and v reset -0.5 v cc1 total output supply voltage (v cc2 - v ee ) -0.5 35 negative output supply voltage (v e - v ee ) -0.5 15 6 positive output supply voltage (v cc2 - v e ) -0.5 35 - (v e - v ee ) gate drive output voltage v o(peak) -0.5 v cc2 collector voltage v c v ee + 5 v v cc2 desat voltage v desat v e v e + 10 output ic power dissipation p o 600 mw 4 input ic power dissipation p i 150 solder reflow temperature profile see package outline drawings section recommended operating conditions parameter symbol min. max. units note operating temperature t a -40 +100 c input supply voltage v cc1 4.5 5.5 volts 28 total output supply voltage (v cc2 - v ee ) 15 30 9 negative output supply voltage (v e - v ee ) 0 15 6 positive output supply voltage (v cc2 - v e ) 15 30 - (v e - v ee ) collector voltage v c v ee + 6 v cc2
9 electrical specifications (dc) unless otherwise noted, all typical values at t a = 25c, v cc1 = 5 v, and v cc2 - v ee = 30 v, v e - v ee = 0 v; all minimum/maximum specifications are at recommended operating conditions. parameter symbol min. typ. max. units test conditions fig. note logic low input voltages v in+l , v in-l , 0.8 v v resetl logic high input voltages v in+h , v in-h , 2.0 v reseth logic low input currents i in+l , i in-l , -0.5 -0.4 ma v in = 0.4 v i resetl fault logic low output i faultl 5.0 12 v fault = 0.4 v 30 current fault logic high output i faulth -40 a v fault = v cc1 31 current high level output current i oh -0.5 -1.5 a v out = v cc2 - 4 v 3, 8, 7 -2.0 v out = v cc2 - 15 v 32 5 low level output current i ol 0.5 2.3 v out = v ee + 2.5 v 4, 9, 7 2.0 v out = v ee + 15 v 33 5 low level output current i olf 90 160 230 ma v out - v ee = 14 v 5, 34 8 during fault condition high level output voltage v oh v c - 3.5 v c - 2.5 v c - 1.5 v i out = -100 ma 6, 8, 9, 10, 11 v c -2.9 v c - 2.0 v c - 1.2 i out = -650 a 35 v c i out = 0 low level output voltage v ol 0.17 0.5 i out = 100 ma 7, 9, 26 36 high level input supply i cc1h 17 22 ma v in+ = v cc1 = 5.5 v, 10, 37 current v in- = 0 v 38 low level input supply i ccil 6 11 v in+ = v in- = 0 v, current v cc1 = 5.5 v output supply current i cc2 2.5 5 v out open 11, 12, 11 39, 40 low level collector current i cl 0.3 1.0 i out = 0 15, 59 27 high level collector current i ch 0.3 1.3 i out = 0 15, 58 27 1.8 3.0 i out = -650 a 15, 57 v e low level supply i el -0.7 -0.4 0 14, 61 current v e high level supply i eh -0.5 -0.14 0 14, 40 25 current blanking capacitor i chg -0.13 -0.25 -0.33 v desat = 0 - 6 v 13, 41 11, 12 charging current -0.18 -0.25 -0.33 v desat = 0 - 6 v, t a = 25c - 100c blanking capacitor i dschg 10 50 v desat = 7 v 42 discharge current uvlo threshold v uvlo+ 11.6 12.3 13.5 v v out > 5 v 43 9, 11, 13 v uvlo- 11.1 12.4 v out < 5 v 9, 11, 14 uvlo hysteresis (v uvlo+ - 0.4 1.2 v uvlo- ) desat threshold v desat 6.5 7.0 7.5 v cc2 - v e > v uvlo - 16, 44 11
10 switching specifications (ac) unless otherwise noted, all typical values at t a = 25c, v cc1 = 5 v, and v cc2 - v ee = 30 v, v e - v ee = 0 v; all minimum/maximum specifications are at recommended operating conditions. parameter symbol min. typ. max. units test conditions fig. note v in to high level output t plh 0.10 0.30 0.50 s rg = 10 17,18,19, 15 propagation delay time cg = 10 nf, 20,21,22, v in to low level output t phl 0.10 0.32 0.50 f = 10 khz, 45,54,55 propagation delay time duty cycle = 50% pulse width distortion pwd -0.30 0.02 0.30 16,17 propagation delay difference (t phl - t plh ) -0.35 0.35 17,18 between any two parts pdd 10% to 90% rise time t r 0.1 45 90% to 10% fall time t f 0.1 desat sense to 90% v out delay t desat(90%) 0.3 0.5 rg = 10 , 23,56 19 cg = 10 nf desat sense to 10% v out delay t desat(10%) 2.0 3.0 v cc2 - v ee = 30 v 24,28, 46,56 desat sense to low level fault t desat(fault) 1.8 5 25,47, 20 signal delay 56 desat sense to desat low t desat(low) 0.25 56 21 propagation delay reset to high level fault signal t reset(fault) 3 7 20 26,27, 22 delay 56 reset signal pulse width pw reset 0.1 uvlo to v out high delay t uvlo on 4.0 v cc2 = 1.0 ms 49 13 uvlo to v out low delay t uvlo off 6.0 ramp 14 output high level common mode |cm h | 15 30 kv/s t a = 25c, 50,51, 23 transient immunity v cm = 1500 v, 52,53 v cc2 = 30 v output low level common mode |cm l | 15 30 t a = 25c, 24 transient immunity v cm = 1500 v, v cc2 = 30 v
11 notes: 1. in accordance with ul1577, each optocoupler is proof tested by applying an insulation test voltage 6000 vrms for 1 second. this test is per- formed before the 100% production test for partial discharge (method b) shown in iec/en/din en 60747-5-2 insulation characteris tic table, if applicable. 2. the input-output momentary with stand voltage is a dielectr ic voltage rating that should not be interpreted as an input-out put continuous voltage rating. for the continuous voltage rating refer to your equipment level safety specification or iec/en/din en 60747-5-2 insulation characteristics table. 3. device considered a two terminal device: pins 1 - 8 shorted together and pins 9 - 16 shorted together. 4. in order to achieve the absolute maximum power dissipation specified, pins 4, 9, and 10 require ground plane connections an d may require airflow. see the thermal model section in the application notes at the end of this data sheet for details on how to estimate jun ction tem- perature and power dissipation. in most cases the absolute maximum output ic junction temperature is the limiting factor. the a ctual power dissipation achievable will depend on the application environment (pcb layout, air flow, part placement, etc.). see the recommen ded pcb layout section in the application notes for layout considerations . output ic power dissipation is derated linearly at 10 mw/c above 90c. input ic power dissipation does not require derating. 5. maximum pulse width = 10 s, maximum duty cycle = 0.2%. this value is intended to allow for compo nent tolerances for desig ns with i o peak minimum = 2.0 a. see applications section for additional details on i oh peak. derate linearly from 3.0 a at +25c to 2.5 a at +100c. this compensates for increased i opeak due to changes in v ol over temperature. 6. this supply is optional. required only when negative gate drive is implemented. 7. maximum pulse width = 50 s, maximum duty cycle = 0.5%. 8. see the slow igbt gate discharge during fault condition section in the applications notes at the end of this data sheet for further details. 9. 15 v is the recommended minimum operating positive supply voltage (v cc2 - v e ) to ensure adequate margin in excess of the maximum v u- vlo+ threshold of 13.5 v. for high level output voltage testing, v oh is measured with a dc load current. when driving capacitive loads, v oh will approach v cc as i oh approaches zero units. 10. maximum pulse width = 1.0 ms, maximum duty cycle = 20%. 11. once v out of the hcpl-316j is allowed to go high (v cc2 - v e > v uvlo ), the desat detection feature of the hcpl-316j will be the primary source of igbt protection. uvlo is needed to ensure desat is functional. once v uvlo+ > 11.6 v, desat will remain functional until v uvlo- < 12.4 v. thus, the desat detection and uvlo features of the hcpl-316j work in conjunction to ensure constant igbt protection. 12. see the blanking time control section in the applications notes at the end of this data sheet for further details. 13. this is the increasing (i.e. turn-on or positive going direction) of v cc2 - v e . 14. this is the decreasing (i.e. turn-off or negative going direction) of v cc2 - v e . 15. this load condition approximates the gate load of a 1200 v/75a igbt. 16. pulse width distortion (pwd) is defined as |t phl - t plh | for any given unit. 17. as measured from v in+ , v in- to v out . 18. the difference between t phl and t plh between any two hcpl-316j parts under the same test conditions. 19. supply voltage dependent. 20. this is the amount of time from when the desat threshold is exceeded, until the fault output goes low. 21. this is the amount of time the desat threshold must be exceeded before v out begins to go low, and the fault output to go low. 22. this is the amount of time from when reset is asserted low, until fault output goes high. the minimum specification of 3 s is the guaran- teed minimum fault signal pulse width when the hcpl-316j is configured for auto-reset. see the auto-reset section in the applica tions notes at the end of this data sheet for further details. 23. common mode transient immunity in the high state is the maximum tolerable dv cm /dt of the common mode pulse, v cm , to assure that the output will remain in the high state (i.e., v o > 15 v or fault > 2 v). a 100 pf and a 3k pull-up resistor is needed in fault detection mode. 24. common mode transient immunity in the low state is the maximum tolerable dv cm /dt of the common mode pulse, v cm , to assure that the output will remain in a low state (i.e., v o < 1.0 v or fault < 0.8 v). 25. does not include led2 current during fault or blanking capacitor discharge current. 26. to clamp the output voltage at v cc - 3 v be , a pull-down resistor between the output and v ee is recommended to sink a static current of 650 a while the output is high. see the output pull-down resistor section in the application notes at the end of this data sheet i f an output pull- down resistor is not used. 27. the recommended output pull-down resistor between v out and v ee does not contribute any output current when v out = v ee . 28. in most applications v cc1 will be powered up first (before v cc2 ) and powered down last (after v cc2 ). this is desirable for maintaining control of the igbt gate. in applications where v cc2 is powered up first, it is important to ensure that v in+ remains low until v cc1 reaches the proper operating voltage (minimum 4.5 v) to avoid any momentary instability at the output during v cc1 ramp-up or ramp-down.
12 performance plots figure 3. i oh vs. temperature. figure 5. i olf vs. v out . figure 6. v oh vs. temperature. figure 7. v ol vs. temperature. figure 8. v oh vs. i oh . figure 9: v ol vs. i ol . figure 10. i cc1 vs. temperature. figure 11: i cc2 vs. t emperature. figure 4. i ol vs. temperature. i oh C output high current C a -40 1.0 t a C temperature C c 100 1.8 1.6 -20 2.0 02040 1.2 60 80 1.4 i ol C output low current -40 0 t a C temperature C c 100 6 4 -20 7 02040 2 80 v out = v ee + 15 v v out = v ee + 2.5 v 60 1 3 5 (v oh -v cc ) C high output voltage drop C v -40 -4 t a C temperature C c 100 -20 0 02040 80 i out = -650 a i out = -100 ma 60 -3 -2 -1 i cc2 C output supply current C ma -40 2.2 t a C temperature C c 100 -20 2.6 02040 80 i cc2h i cc2l 60 2.3 2.4 2.5 v ol C output low voltage C v -40 0 t a C temperature C c 100 0.20 0.15 -20 0.25 02040 0.05 60 80 0.10 i out = 100 ma i cc1 C supply current C ma -40 0 t a C temperature C c 100 -20 20 02040 80 i cc1h i cc1l 60 5 10 15 v oh C output high voltage C v 0 27.4 i oh C output high current C a 1.0 28.6 28.4 29.0 0.4 27.8 0.6 28.0 0.2 0.8 27.6 28.2 28.8 +100c +25c -40c i olf C low level output current during fault condition C ma 0 25 v out C output voltage C v 30 175 125 5 200 10 25 15 50 100 150 75 20 -40c 25c 100c v ol C output low voltage C v 0.1 0 i ol C output low current C a 0.5 6 1.0 1.5 2.0 2.5 3 4 5 2 1 +100c +25c -40c
13 figure 12. i cc2 vs. v cc2 . figure 13. i chg vs. temperature. figure 14. i e vs. temperature. figure 15. i c vs. i out . figure 16. desat threshold vs. temperature. f igure 17. propagation delay vs. temperature. figure 18. propagation delay vs. supply voltage. figure 19. v in to high propagation delay vs. temperature. figure 20. v in to low propagation delay vs. temperature. i cc2 C output supply current C ma 15 2.35 v cc2 C output supply voltage C v 30 2.55 2.50 2.60 20 2.40 25 2.45 i cc2h i cc2l i chg C blanking capacitor charging current C ma -40 -0.30 t a C temperature C c 100 -20 -0.15 02040 80 60 -0.25 -0.20 v desat C desat threshold C v -40 6.0 t a C temperature C c 100 -20 7.5 02040 80 60 7.0 6.5 t p C propagation delay C s -40 0.2 t a C temperature C c 100 -20 0.5 02040 80 60 0.4 0.3 t phl t plh t p C propagation delay C s 15 0.20 v cc C supply voltage C v 30 0.40 20 25 0.25 0.30 0.35 t phl t plh propagation delay C s 0.25 temperature C c 0.45 0 50 100 0.30 0.35 0.40 v cc1 = 5.5 v v cc1 = 5.0 v v cc1 = 4.5 v -50 propagation delay C s 0.25 temperature C c 0.50 0 50 100 0.40 0.45 v cc1 = 5.5 v v cc1 = 5.0 v v cc1 = 4.5 v 0.30 0.35 -50 ic (ma) 0 0 i out (ma) 2.0 4 0.5 1.0 1.5 2 3 1 -40c +25c +100c i e -v e supply current C ma -40 0.30 t a C temperature C c 100 -20 0.50 02040 80 i eh i el 60 0.40 0.45 0.35
14 figure 21. propagation delay vs. load capaci- tance. figure 22. propagation delay vs. load resistance. figure 23. desat sense to 90% v out delay vs. temperature. figure 24. desat sense to 10% v out delay vs. temperature. figure 25. desat sense to low level fault signal delay vs. temperature. figure 26. desat sense to 10% v out delay vs. load capacitance. figure 27. desat sense to 10% v out delay vs. load resistance. figure 28. reset to high level fault signal delay vs. temperature. delay C s 0.25 temperature C c 0.45 0 100 0.30 0.35 0.40 50 -50 delay C s 1.0 temperature C c 3.0 0 100 1.5 2.0 2.5 50 v cc2 = 15 v v cc2 = 30 v -50 delay C s 1.6 temperature C c 2.6 0 50 100 2.2 2.4 1.8 2.0 -50 v ee = 0 v v ee = -5 v v ee = -10 v v ee = -15 v delay C s 0.0010 load resistance C 50 0.0030 10 20 40 0.0015 0.0020 0.0025 30 v cc2 = 15 v v cc2 = 30 v delay C s 4 temperature C c 150 12 0 50 100 6 8 10 v cc1 = 5.5 v v cc1 = 5.0 v v cc1 = 4.5 v -50 delay C s 0.20 load capacitance C nf 100 0.40 20 40 80 0.25 0.30 0.35 t plh t phl 060 delay C s 0.20 load resistance C 50 0.40 10 20 40 0.25 0.30 0.35 t plh t phl 030 delay C ms 0 load capacitance C nf 50 0.008 10 20 40 0.002 0.004 0.006 030 v cc2 = 15 v v cc2 = 30 v
15 test circuit diagrams figure 32. i oh pulsed test circuit. figure 33. i ol pulsed test circuit. figure 34. i olf test circuit. figure 35. v oh pulsed test circuit. figure 31. i faulth test circuit. figure 30. i faultl test circuit. 0.1 f + C 10 ma v e v led2+ desat v cc2 v c v out v ee v ee v in+ v in- v cc1 gnd1 reset fault v led1+ v led1- 0.1 f 4.5 v i fault C + 0.4 v + C v e v led2+ desat v cc2 v c v out v ee v ee v in+ v in- v cc1 gnd1 reset fault v led1+ v led1- 0.1 f 5 v 5 v + C i fault 0.1 f + C 0.1 f v e v led2+ desat v cc2 v c v out v ee v ee v in+ v in- v cc1 gnd1 reset fault v led1+ v led1- 0.1 f 5 v + C + C + C 30 v 30 v 15 v pulsed 0.1 f i out 0.1 f 0.1 f v e v led2+ desat v cc2 v c v out v ee v ee v in+ v in- v cc1 gnd1 reset fault v led1+ v led1- + C + C + C 30 v 30 v 15 v pulsed 0.1 f i out 0.1 f 0.1 f v e v led2+ desat v cc2 v c v out v ee v ee v in+ v in- v cc1 gnd1 reset fault v led1+ v led1- + C + C + C 30 v 30 v 14 v 0.1 f i out + C 0.1 f 5 v 0.1 f + C 0.1 f v e v led2+ desat v cc2 v c v out v ee v ee v in+ v in- v cc1 gnd1 reset fault v led1+ v led1- 0.1 f 5 v + C + C 30 v 30 v 0.1 f v out 2a pulsed
16 figure 36. v ol test circuit. figure 37. i cc1h test circuit. figure 38. i cc1l test circuit. figure 39. i cc2h test circuit. figure 40. i cc2l test circuit. figure 41. i chg pulsed test circuit. 0.1 f + C 0.1 f v e v led2+ desat v cc2 v c v out v ee v ee v in+ v in- v cc1 gnd1 reset fault v led1+ v led1- 0.1 f 5 v + C + C 30 v 30 v 0.1 f v out 100 ma + C v e v led2+ desat v cc2 v c v out v ee v ee v in+ v in- v cc1 gnd1 reset fault v led1+ v led1- 0.1 f 5.5 v i cc1 + C v e v led2+ desat v cc2 v c v out v ee v ee v in+ v in- v cc1 gnd1 reset fault v led1+ v led1- 0.1 f 5.5 v i cc1 0.1 f 0.1 f v e v led2+ desat v cc2 v c v out v ee v ee v in+ v in- v cc1 gnd1 reset fault v led1+ v led1- + C + C 30 v 30 v i cc2 0.1 f + C 5 v 0.1 f 0.1 f 0.1 f v e v led2+ desat v cc2 v c v out v ee v ee v in+ v in- v cc1 gnd1 reset fault v led1+ v led1- + C + C 30 v 30 v i cc2 0.1 f 0.1 f 0.1 f v e v led2+ desat v cc2 v c v out v ee v ee v in+ v in- v cc1 gnd1 reset fault v led1+ v led1- + C + C 30 v 30 v i chg 0.1 f + C 5 v 0.1 f
17 figure 42. i dschg test circuit. figure 43. uvlo threshold test circuit. figure 44. desat threshold test circuit. figure 45. t plh , t phl , t r , t f test circuit. figure 46. t desat(10%) test circuit. figure 47. t desat(fault) test circuit. 0.1 f 0.1 f v e v led2+ desat v cc2 v c v out v ee v ee v in+ v in- v cc1 gnd1 reset fault v led1+ v led1- + C + C 30 v 30 v i dschg + C 7 v 0.1 f + C v e v led2+ desat v cc2 v c v out v ee v ee v in+ v in- v cc1 gnd1 reset fault v led1+ v led1- 0.1 f 5 v + C sweep 0.1 f v out 0.1 f 0.1 f v e v led2+ desat v cc2 v c v out v ee v ee v in+ v in- v cc1 gnd1 reset fault v led1+ v led1- 0.1 f + C + C 15 v 15 v sweep 0.1 f + C 10 ma 0.1 f 0.1 f v e v led2+ desat v cc2 v c v out v ee v ee v in+ v in- v cc1 gnd1 reset fault v led1+ v led1- 0.1 f 5 v + C + C 30 v 30 v v out 0.1 f 10 nf 10 + C v in 3 k 0.1 f 0.1 f v e v led2+ desat v cc2 v c v out v ee v ee v in+ v in- v cc1 gnd1 reset fault v led1+ v led1- 0.1 f 5 v + C + C 30 v 30 v v out 0.1 f 10 nf 10 3 k v in + C 0.1 f 0.1 f v e v led2+ desat v cc2 v c v out v ee v ee v in+ v in- v cc1 gnd1 reset fault v led1+ v led1- 0.1 f 5 v + C + C 30 v 30 v 0.1 f 10 nf 10 3 k v in + C v fault
18 figure 49. uvlo delay test circuit. figure 50. cmr test circuit, led2 off. figure 51. cmr test circuit, led2 on. figure 52. cmr test circuit, led1 off. figure 53. cmr test circuit, led1 on. figure 48. t reset(fault) test circuit. 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 v e v led2+ desat v cc2 v c v out v ee v ee v in+ v in- v cc1 gnd1 reset fault v led1+ v led1 scope 3 k 100 pf 0.1 f 10 0.1 f 10 nf v cm 5 v 25 v 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 v e v led2+ desat v cc2 v c v out v ee v ee v in+ v in- v cc1 gnd1 reset fault v led1+ v led1 scope 3 k 100 pf 0.1 f 10 10 nf v cm + C 750 9 v 25 v 5 v 0.1 f 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 v e v led2+ desat v cc2 v c v out v ee v ee v in+ v in- v cc1 gnd1 reset fault v led1+ v led1 3 k 100 pf 0.1 f 10 10 nf v cm 0.1 f scope 25 v 5 v 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 v e v led2+ desat v cc2 v c v out v ee v ee v in+ v in- v cc1 gnd1 reset fault v led1+ v led1 scope 3 k 100 pf 0.1 f 10 10 nf v cm 0.1 f 25 v 5 v 0.1 f 0.1 f v e v led2+ desat v cc2 v c v out v ee v ee v in+ v in- v cc1 gnd1 reset fault v led1+ v led1- 0.1 f 5 v + C + C 30 v 30 v 0.1 f 10 nf 10 3 k strobe 8 v + C v fault v in high to low v e v led2+ desat v cc2 v c v out v ee v ee v in+ v in- v cc1 gnd1 reset fault v led1+ v led1- 0.1 f 5 v v out 0.1 f 10 nf 10 3 k + C r amp
19 figure 54. v out propagation delay waveforms, noninverting configuration. figure 55. v out propagation delay waveforms, inverting configuration. figure 56. desat, v out , fault, reset delay waveforms. v in+ v out t phl t plh t f t r 10% 50% 90% v in- 2.5 v 2.5 v 0 v v in+ v out t phl t plh t f t r 10% 50% 90% v in- 2.5 v 2.5 v 5.0 v v out t reset (fault) 50% (2.5 v) 50% 10% 7 v 50% t desat (fault) v desat fault reset t desat (90%) t desat (low) t desat (10%) 90%
20 figure 57. i ch test circuit. figure 58. i ch test circuit. figure 59. i cl test circuit. figure 60. i eh test circuit. figure 61. i el test circuit. 0.1 f 0.1 f v e v led2+ desat v cc2 v c v out v ee v ee v in+ v in- v cc1 gnd1 reset fault v led1+ v led1- + C + C 30 v 30 v 650 a 0.1 f i c + C 0.1 f 5 v 0.1 f 0.1 f v e v led2+ desat v cc2 v c v out v ee v ee v in+ v in- v cc1 gnd1 reset fault v led1+ v led1- + C + C 30 v 30 v 0.1 f i c + C 0.1 f 5 v 0.1 f 0.1 f v e v led2+ desat v cc2 v c v out v ee v ee v in+ v in- v cc1 gnd1 reset fault v led1+ v led1- + C + C 30 v 30 v 0.1 f i c 0.1 f 0.1 f v e v led2+ desat v cc2 v c v out v ee v ee v in+ v in- v cc1 gnd1 reset fault v led1+ v led1- + C + C 30 v 30 v 0.1 f i e + C 0.1 f 5 v 0.1 f 0.1 f v e v led2+ desat v cc2 v c v out v ee v ee v in+ v in- v cc1 gnd1 reset fault v led1+ v led1- + C + C 30 v 30 v 0.1 f i e + C 0.1 f 5 v
21 typical application/operation introduction to fault detection and protection the power stage of a typical three phase inverter is sus- ceptible to several types of failures, most of which are potentially destructive to the power igbts. these failure modes can be grouped into four basic categories: phase and/or rail supply short circuits due to user misconnect or bad wiring, control signal failures due to noise or com- putational errors, overload conditions induced by the load, and component failures in the gate drive circuitry. under any of these fault conditions, the current through the igbts can increase rapidly, causing excessive power dissipation and heating. the igbts become damaged when the current load approaches the saturation cur- rent of the device, and the collector to emitter voltage rises above the saturation voltage level. the drastically increased power dissipation very quickly overheats the power device and destroys it. to prevent damage to the drive, fault protection must be implemented to reduce or turn-off the overcurrents during a fault condition. a circuit providing fast local fault detection and shut- down is an ideal solution, but the number of required components, board space consumed, cost, and complex- ity have until now limited its use to high performance drives. the features which this circuit must have are high speed, low cost, low resolution, low power dissipation, and small size. applications information the hcpl-316j satisfies these cri- teria by combining a high speed, high output current driver, high voltage optical isolation between the input and output, local igbt desaturation detection and shut down, and an optically isolated fault status feedback sig- nal into a single 16-pin surface mount package. the fault detection method, which is adopted in the hcpl-316j, is to monitor the saturation (collector) volt- age of the igbt and to trigger a local fault shutdown se- quence if the collector voltage exceeds a predetermined threshold. a small gate discharge device slowly reduces the high short circuit igbt current to prevent damaging voltage spikes. before the dissipated energy can reach destructive levels, the igbt is shut off. during the off state of the igbt, the fault detect circuitry is simply dis- abled to prevent false fault signals. the alternative protection scheme of measuring igbt current to prevent desaturation is effective if the short circuit capability of the power device is known, but this method will fail if the gate drive voltage decreases enough to only partially turn on the igbt. by directly measuring the collector voltage, the hcpl-316j limits the power dissipation in the igbt even with insufficient gate drive voltage. another more subtle advantage of the desaturation detection method is that power dissi- pation in the igbt is monitored, while the current sense method relies on a preset current threshold to predict the safe limit of operation. therefore, an overly- conser- vative overcurrent threshold is not needed to protect the igbt. recommended application circuit the hcpl-316j has both inverting and non-inverting gate control inputs, an active low reset input, and an open collector fault output suitable for wired or appli- cations. the recommended application circuit shown in figure 62 illustrates a typical gate drive implementation using the hcpl-316j. the four supply bypass capacitors (0.1 f) provide the large transient currents necessary during a switching transition. because of the transient nature of the charg- ing currents, a low current (5 ma) power supply suffices. the desat diode and 100 pf capacitor are the necessary external components for the fault detection circuitry. the gate resistor (10 ) serves to limit gate charge cur- rent and indirectly control the igbt collector voltage rise and fall times. the open collector fault output has a passive 3.3 k pull-up resistor and a 330 pf filtering capacitor. a 47 k pulldown resistor on v out provides a more predictable high level output voltage (v oh ). in this application, the igbt gate driver will shut down when a fault is detected and will not resume switching until the microcontroller applies a reset signal.
22 figure 62. recommended application circuit. description of operation/timing figure 63 below illustrates input and output waveforms under the conditions of normal operation, a desat fault condition, and normal reset behavior. normal operation during normal operation, v out of the hcpl-316j is con- trolled by either v in+ or v in- , with the igbt collector-to- emitter voltage being monitored through d desat . the fault output is high and the reset input should be held high. see figure 63. figure 63. timing diagram. fault condition when the voltage on the desat pin exceeds 7 v while the igbt is on, v out is slowly brought low in order to softly turn-off the igbt and prevent large di/dt induced voltages. also activated is an internal feedback channel which brings the fault output low for the purpose of notifying the micro-controller of the fault condition. see figure 63. reset the fault output remains low until reset is brought low. see figure 63. while asserting the reset pin (low), the input pins must be asserted for an output low state (v in+ is low or v in- is high). this may be accomplished either by software control (i.e. of the microcontroller) or hardware control (see figures 73 and 74). v out v desat v in+ fault reset normal operation fault condition reset v in+ v in- v in- 5 v 0 v 5 v 5 v 7 v non-inverting configured inputs inverting configured inputs + C + C 100 pf d desat 0.1 f 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 v e v led2+ desat v cc2 v c v out v ee v ee v in+ v in- v cc1 gnd1 reset fault v led1+ v led1- hcpl-316j + C c 3.3 k 0.1 f 5 v 330 pf r g v cc2 = 18 v v ee = -5 v 47 k 3-phase output 0.1 f 0.1 f v f +C q1 q2 v ce + C v ce + C 100
23 slow igbt gate discharge during fault condition when a desaturation fault is detected, a weak pull-down device in the hcpl-316j output drive stage will turn on to softly turn off the igbt. this device slowly discharges the igbt gate to prevent fast changes in drain current that could cause damaging voltage spikes due to lead and wire inductance. during the slow turn off, the large output pull-down device remains off until the output voltage falls below v ee + 2 volts, at which time the large pull down device clamps the igbt gate to v ee . desat fault detection blanking time the desat fault detection circuitry must remain disabled for a short time period following the turn-on of the igbt to allow the collector voltage to fall below the desat theshold. this time period, called the desat blanking time, is controlled by the internal desat charge current, the desat voltage threshold, and the external desat ca- pacitor. the nominal blanking time is calculated in terms of external capacitance (c blank ), fault threshold volt- age (v desat ), and desat charge current (i chg ) as t blank = c blank x v desat / i chg . the nominal blanking time with the recommended 100 pf capacitor is 100 pf * 7 v / 250 a = 2.8 sec. the capacitance value can be scaled slightly to adjust the blanking time, though a value small- er than 100 pf is not recommended. this nominal blank- ing time also represents the longest time it will take for the hcpl-316j to respond to a desat fault condition. if the igbt is turned on while the collector and emitter are shorted to the supply rails (switching into a short), the soft shut-down sequence will begin after approximately 3 sec. if the igbt collector and emitter are shorted to the supply rails after the igbt is already on , the response time will be much quicker due to the parasitic parallel capacitance of the desat diode. the recommended 100 pf capacitor should provide adequate blanking as well as fault response times for most applications. under voltage lockout the hcpl-316j under voltage lockout (uvlo) feature is designed to prevent the application of insufficient gate voltage to the igbt by forcing the hcpl-316j output low during power-up. igbts typically require gate voltages of 15 v to achieve their rated v ce(on) voltage. at gate voltages below 13 v typically, their on-voltage increases dramatically, especially at higher currents. at very low gate voltages (below 10 v), the igbt may operate in the linear region and quickly overheat. the uvlo function causes the output to be clamped whenever insufficient operating supply (v cc2 ) is applied. once v cc2 exceeds v uvlo+ (the positive-going uvlo threshold), the uvlo clamp is released to allow the device output to turn on in response to input signals. as v cc2 is increased from 0 v (at some level below v uvlo+ ), first the desat protection circuitry becomes active. as v cc2 is further increased (above v uvlo+ ), the uvlo clamp is released. before the time the uvlo clamp is released, the desat protection is already active. therefore, the uvlo and desat fault detection features work together to provide seamless protection regardless of supply voltage (v cc2 ).
24 behavioral circuit schematic the functional behavior of the hcpl-316j is rep- resented by the logic diagram in figure 64 which fully describes the interaction and se- quence of internal and external signals in the hcpl-316j. input ic in the normal switching mode, no output fault has been detected, and the low state of the fault latch allows the input signals to control the signal led. the fault output is in the open-collector state, and the state of the reset pin does not affect the control of the igbt gate. when a fault is detected, the fault output and signal input are both latched. the fault output changes to an active low state, and the signal led is forced off (output low). the latched condition will persist until the reset pin is pulled low. figure 64. behavioral circuit schematic. output ic three internal signals control the state of the driver out- put: the state of the signal led, as well as the uvlo and fault signals. if no fault on the igbt collector is detected, and the supply voltage is above the uvlo threshold, the led signal will control the driver output state. the driver stage logic includes an interlock to ensure that the pull-up and pull-down devices in the output stage are never on at the same time. if an undervoltage condition is detected, the output will be actively pulled low by the 50x dmos device, regardless of the led state. if an igbt desaturation fault is detected while the signal led is on, the fault signal will latch in the high state. the triple dar- lington and the 50x dmos device are disabled, and a smaller 1x dmos pull-down device is activated to slowly discharge the igbt gate. when the output drops below two volts, the 50x dmos device again turns on, clamp- ing the igbt gate firmly to vee. the fault signal remains latched in the high state until the signal led turns off. v in+ (1) v inC (2) v cc1 (3) gnd (4) fault (6) reset (5) delay rs q fault led 12 v + C v cc2 (13) 7 v C + desat (14) v e (16) 250 a v c (12) v out (11) v ee (9,10) 50 x 1 x fault uvlo
25 other recommended components the application circuit in figure 62 includes an output pull-down resistor, a desat pin protection resistor, a fault pin capacitor (330 pf), and a fault pin pull-up resistor. output pull-down resistor during the output high transition, the output voltage rapidly rises to within 3 diode drops of v cc2 . if the output current then drops to zero due to a capacitive load, the output voltage will slowly rise from roughly v cc2 -3(v be ) to v cc2 within a period of several microseconds. to limit the output voltage to v cc2 -3(v be ), a pull-down resistor between the output and v ee is recommended to sink a static current of several 650 a while the output is high. pull-down resistor values are dependent on the amount of positive supply and can be adjusted according to the formula, r pull-down = [v cc2 -3 * (v be )] / 650 a. desat pin protection the freewheeling of flyback diodes connected across the igbts can have large instantaneous forward voltage transients which greatly exceed the nominal forward voltage of the diode. this may result in a large negative voltage spike on the desat pin which will draw substan- tial current out of the ic if protection is not used. to limit this current to levels that will not damage the ic, a 100 ohm resistor should be inserted in series with the de- sat diode. the added resistance will not alter the desat threshold or the desat blanking time. capacitor on fault pin for high cmr rapid common mode transients can affect the fault pin voltage while the fault output is in the high state. a 330 pf capacitor (fig. 66) should be connected between the fault pin and ground to achieve adequate cmos noise margins at the specified cmr value of 15 kv/s. the added capacitance does not increase the fault out- put delay when a desaturation condition is detected. pull-up resistor on fault pin the fault pin is an open-collector output and therefore requires a pull-up resistor to provide a high-level signal. driving with standard cmos/ttl for high cmr capacitive coupling from the isolated high voltage circuitry to the input referred circuitry is the primary cmr limitation. this coupling must be accounted for to achieve high cmr perform ance. the input pins v in+ and v in- must have active drive signals to prevent unwanted switching of the output under extreme common mode transient conditions. input drive circuits that use pull-up or pull-down resistors, such as open collector configu- rations, should be avoided. standard cmos or ttl drive circuits are recommended. figure 65. output pull-down resistor. figure 66. desat pin protection. figure 67. fault pin cmr protection. 16 15 14 13 12 11 10 9 v e v led2+ desat v cc2 v c v out v ee v ee 100 hcpl-316j 100 pf d desat r g 1 2 3 4 5 6 7 8 v in+ v in- v cc1 gnd1 reset fault v led1+ v led1- hcpl-316j + C c 330 pf 3.3 k 16 15 14 13 12 11 10 9 v e v led2+ desat v cc2 v c v out v ee v ee hcpl-316j r g r pull-down
26 user-configuration of the hcpl-316j input side the v in+ , v in- , fault and reset input pins make a wide variety of gate control and fault configurations pos- sible, depending on the motor drive requirements. the hcpl-316j has both inverting and non inverting gate control inputs, an open collector fault output suitable for wired or applications and an active low reset input. driving input pf hcpl-316j in non-inverting/inverting mode the gate drive voltage output of the hcpl-316j can be configured as inverting or non-inverting using the v inC and v in+ inputs. as shown in figure 68, when a non-inverting configuration is desired, v inC is held low by connecting it to gnd1 and v in+ is toggled. as shown in figure 69, when an inverting configuration is desired, v in+ is held high by connecting it to v cc1 and v inC is tog- gled. local shutdown, local reset as shown in figure 70, the fault output of each hcpl- 316j gate driver is polled separately, and the individual reset lines are asserted low independently to reset the motor controller after a fault condition. global-shutdown, global reset as shown in figure 71, when configured for inverting op- eration, the hcpl-316j can be configured to shutdown automatically in the event of a fault condition by tying the fault output to v in+ . for high reliability drives, the open collector fault outputs of each hcpl-316j can be wire ored together on a common fault bus, forming a single fault bus for interfacing directly to the micro-con- troller. when any of the six gate drivers detects a fault, the fault output signal will disable all six hcpl-316j gate drivers simultaneously and thereby provide protection against further catastrophic failures. figure 68. typical input configuration, noninverting. figure 69. typical input configuration, inverting. figure 70. local shutdown, local reset configuration. 1 2 3 4 5 6 7 8 v in+ v in- v cc1 gnd1 reset fault v led1+ v led1- hcpl-316j + C c 1 2 3 4 5 6 7 8 v in+ v in- v cc1 gnd1 reset fault v led1+ v led1- hcpl-316j + C c 1 2 3 4 5 6 7 8 v in+ v in- v cc1 gnd1 reset fault v led1+ v led1- hcpl-316j + C c
27 figure 71. global-shutdown, global reset configuration. figure 72. auto-reset configuration. auto-reset as shown in figure 72, when the inverting v in- input is connected to ground (non-inverting configuration), the hcpl-316j can be configured to reset automatically by connecting reset to v in+ . in this case, the gate control signal is applied to the non-inverting input as well as the reset input to reset the fault latch every switching cycle. during normal operation of the igbt, asserting the reset input low has no effect. following a fault condition, the gate driver remains in the latched fault state until the gate control signal changes to the gate low state and resets the fault latch. if the gate control signal is a con- tinuous pwm signal, the fault latch will always be reset by the next time the input signal goes high. this config- uration protects the igbt on a cycle-by-cycle basis and automatically resets before the next on cycle. the fault outputs can be wire ored together to alert the micro- controller, but this signal would not be used for control purposes in this (auto-reset) configuration. when the hcpl- 316j is configured for auto-reset, the guaranteed minimum fault signal pulse width is 3 s. figure 73a. safe hardware reset for noninverting input configuration (automatically resets for every v in+ input). figure 73b. safe hardware reset for noninverting input configuration. resetting following a fault condition to resume normal switching operation following a fault condition (fault output low), the reset pin must first be asserted low in order to release the internal fault latch and reset the fault output (high). prior to assert- ing the reset pin low, the input (v in ) switching signals must be configured for an output (v ol ) low state. this can be handled directly by the microcontroller or by hardwiring to synchronize the reset signal with the ap- propriate input signal. figure 73a shows how to connect the reset to the v in+ signal for safe automatic reset in the noninverting input configuration. figure 73b shows how to configure the v in+ /reset signals so that a reset signal from the microcontroller causes the input to be in the output-off state. similarly, figures 73c and 73d show automatic reset and microcontroller reset safe configurations for the inverting input configuration. 1 2 3 4 5 6 7 8 v in+ v in- v cc1 gnd1 reset fault v led1+ v led1- hcpl-316j + C c connect to other faults connect to other resets hcpl-316j fig 72 1 2 3 4 5 6 7 8 v in+ v in- v cc1 gnd1 reset fault v led1+ v led1- hcpl-316j + C c 1 2 3 4 5 6 7 8 v in+ v in- v cc1 gnd1 reset fault v led1+ v led1- hcpl-316j c v cc v in+ / reset fault 1 2 3 4 5 6 7 8 v in+ v in- v cc1 gnd1 reset fault v led1+ v led1- hcpl-316j c v cc reset fault v in+
28 0.5 a, the value of r c can be estimated in the following way: r c + r g = [ v cc2 C v oh C ( v ee )] i oh,peak = [4 v C (-5 v)] 0.5 a = 18 r c = 8 see power and layout considerations section for more information on calculating value of r g . user-configuration of the hcpl-316j output side r g and optional resistor r c : the value of the gate resistor r g (along with v cc2 and v ee ) determines the maximum amount of gate-charging/dis- charging current (i on,peak and i off,peak ) and thus should be carefully chosen to match the size of the igbt being driven. often it is desirable to have the peak gate charge current be somewhat less than the peak discharge cur- rent (i on,peak < i off,peak ). for this condition, an optional resistor (r c ) can be used along with r g to independently determine i on,peak and i off,peak without using a steering diode. as an example, refer to figure 74. assuming that r g is already determined and that the design i oh,peak = figure 73d. safe hardware reset for inverting input configuration (automatically resets for every v in- input). figure 73c. safe hardware reset for inverting input configuration. figure 74. use of r c to further limit i on,peak . 16 15 14 13 12 11 10 9 v e v led2+ desat v cc2 v c v out v ee v ee 10 hcpl-316j 100 pf r c 8 10 nf -5 v 15 v 1 2 3 4 5 6 7 8 v in+ v in- v cc1 gnd1 reset fault v led1+ v led1- hcpl-316j c v cc reset fault v in- v cc 1 2 3 4 5 6 7 8 v in+ v in- v cc1 gnd1 reset fault v led1+ v led1- hcpl-316j c v cc reset fault v in- v cc
29 figure 75. current buffer for increased drive current. power/layout considerations operating within the maximum allowable power ratings (adjusting value of r g ): when choosing the value of r g , it is important to con- firm that the power dissipation of the hcpl-316j is within the maximum allowable power rating. the steps for doing this are: 1. calculate the minimum desired r g ; higher output current using an external current buf- fer: to increase the igbt gate drive current, a non-inverting current buffer (such as the npn/pnp buffer shown in figure 75) may be used. inverting types are not com- patible with the desatura-tion fault protection circuitry and should be avoided. to preserve the slow igbt turn- off feature during a fault condition, a 10 nf capacitor should be connected from the buffer input to v ee and a 10 resistor inserted between the output and the common npn/pnp base. the mjd44h11/mjd45h11 pair is appropriate for currents up to 8a maximum. the d44vh10/ d45vh10 pair is appropriate for currents up to 15 a maximum. desat diode and desat threshold the desat diodes function is to conduct forward cur- rent, allowing sensing of the igbts saturated collector- to-emitter voltage, v cesat , (when the igbt is on) and to block high voltages (when the igbt is off). during the short period of time when the igbt is switching, there is commonly a very high dv ce /dt voltage ramp rate across the igbts collector-to-emitter. this results in i charge (= c d-desat x dv ce /dt) charging current which will charge the blanking capacitor, c blank . in order to minimize this charging current and avoid false desat triggering, it is best to use fast response diodes. listed in the be- low table are fast-recovery diodes that are suitable for use as a desat diode (d desat ). in the recommended ap- plication circuit shown in figure 62, the voltage on pin 14 (desat) is v desat = v f + v ce , (where v f is the forward on voltage of d desat and v ce is the igbt collector-to- emitter voltage). the value of v ce which triggers desat to signal a fault condition, is nominally 7v C v f . if de- sired, this desat threshold voltage can be decreased by using multiple desat diodes in series. if n is the number of desat diodes then the nominal threshold value be- comes v ce,fault(th) = 7 v C n x v f . in the case of using two diodes instead of one, diodes with half of the total re- quired maximum reverse-voltage rating may be chosen. max. reverse voltage part number manufacturer t rr (ns) rating, v rrm (volts) package type mur1100e motorola 75 1000 59-04 (axial leaded) murs160t3 motorola 75 600 case 403a (surface mount) uf4007 general semi. 75 1000 do-204al (axial leaded) bym26e philips 75 1000 sod64 (axial leaded) byv26e philips 75 1000 sod57 (axial leaded) byv99 philips 75 600 sod87 (surface mount) 16 15 14 13 12 11 10 9 v e v led2+ desat v cc2 v c v out v ee v ee 10 hcpl-316j 100 pf 10 nf mjd44h11 or d44vh10 4.5 2.5 mjd45h11 or d45vh10 15 v -5 v 2. calculate total power dissipation in the part referring to figure 77. (average switching energy supplied to hcpl-316j per cycle vs. r g plot); 3. compare the input and output power dissipation calculated in step #2 to the maximum recommended dissipation for the hcpl-316j. (if the maximum rec- ommended level has been exceeded, it may be nec- essary to raise the value of r g to lower the switching power and repeat step #2.)
30 p o(bias) = steady-state power dissipation in the hc- pl-316j due to biasing the device. p o(switch) = transient power dissipation in the hc- pl-316j due to charging and discharging power device gate. e switch = average energy dissipated in hcpl-316j due to switching of the power device over one switching cycle (j/cycle). f switch = average carrier signal frequency. for r g = 10.5, the value read from figure 77 is e switch = 6.05 j. assume a worst-case average i cc1 = 16.5 ma (which is given by the average of i cc1h and i cc1l ). simi- larly the average i cc2 = 5.5 ma. p i = 16.5 ma * 5.5 v = 90.8 mw p o = p o(bias) + p o,switch = 5.5 ma * (18 v C (C5 v)) + 6.051 j * 15 khz = 126.5 mw + 90.8 mw = 217.3 mw step 3 : compare the calculated power dissipation with the abso- lute maximum values for the hcpl-316j: for the example, p i = 90.8 mw < 150 mw (abs. max.) ok p o = 217.3 mw < 600 mw (abs. max.) ok therefore, the power dissipation absolute maximum rating has not been exceeded for the example. please refer to the following thermal model section for an explanation on how to calculate the maximum junc- tion temperature of the hcpl-316j for a given pc board layout configuration. as an example, the total input and output power dis- sipation can be calculated given the following condi- tions: ? i on, max ~ 2.0 a ? v cc2 = 18 v ? v ee = -5 v ? f carrier = 15 khz step 1 : calculate r g minimum from i ol peak specification: to find the peak charging l ol assume that the gate is initially charged the steady-state value of v ee . therefore apply the following relationship: [v oh @650 a C (v ol +v ee )] r g = i ol,peak [v cc2 C 1 C (v ol + v ee )] = i ol,peak 18 v C 1 v C (1.5 v + (-5 v)) = 2.0 a = 10.25 10.5 (for a 1% resistor) (note from figure 76 that the real value of i ol may vary from the value calculated from the simple model shown.) step 2 : calculate total power dissipation in the hcpl-316j: the hcpl-316j total power dissipation (p t ) is equal to the sum of the input-side power (p i ) and output-side power (p o ): p t = p i + p o p i = i cc1 * v cc1 p o = p o(bias) + p o,swtich = i cc2 * (v cc2 Cv ee ) + e switch * f switch where, figure 76. typical peak i on and i off currents vs. rg (for hcpl-316j output driving an igbt rated at 600 v/100 a. figure 77. switching energy plot for calculating average pswitch (for hcpl-316j output driving an igbt rated at 600 v/100 a). i on , i off (a) 0 -3 rg ( ) 200 3 1 4 20 100 -1 140 -2 0 2 i off (max.) max. i on , i off v s . gate resistance (v cc2 / v ee2 = 25 v / 5 v 40 60 80 120 160 180 i on (max.) e ss (j) 0 0 rg ( ) 200 8 5 9 50 100 3 150 1 4 7 e ss (qg = 650 nc) 6 2 switching energy v s . gate resistance (v cc2 / v ee2 = 25 v / 5 v
31 figure 78. hcpl-316j thermal model. t ji = junction temperature of input side ic t jo = junction temperature of output side ic t p4 = pin 4 temperature at package edge t p9,10 = pin 9 and 10 temperature at package edge i4 = input side ic to pin 4 thermal resistance i9,10 = output side ic to pin 9 and 10 thermal resistance 4a = pin 4 to ambient thermal resistance 9,10a = pin 9 and 10 to ambient thermal resistance *the 4a and 9,10a values shown here are for pcb layouts shown in figure 78 with reasonable air flow. this value may increase or decrease by a factor of 2 depending on pcb layout and/or airflow. thermal model the hcpl-316j is designed to dissipate the majority of the heat through pins 4 for the input ic and pins 9 and 10 for the output ic. (there are two v ee pins on the output side, pins 9 and 10, for this purpose.) heat flow through other pins or through the package directly into ambient are considered negligible and not modeled here. in order to achieve the power dissipation specified in the absolute maximum specification, it is imperative that pins 4, 9, and 10 have ground planes connected to them. as long as the maximum power specification is not exceeded, the only other limita tion to the amount of power one can dissipate is the absolute maximum junction temperature specification of 125c. the junc- tion temperatures can be calculated with the following equations: t ji = p i ( i4 + 4a ) + t a t jo = p o ( o9,10 + 9,10a ) + t a where p i = power into input ic and p o = power into out- put ic. since 4a and 9,10a are dependent on pcb layout and airflow, their exact number may not be available. therefore, a more accurate method of calcu lat ing the junction temperature is with the following equations: t ji = p i i4 + t p4 t jo = p o o9,10 + t p9,10 these equations, however, require that the pin 4 and pins 9, 10 temperatures be measured with a thermal couple on the pin at the hcpl-316j package edge. from the earlier power dissipation calculation example: p i = 90.8 mw, p o = 217.3 mw, t a = 100c, and assuming the thermal model shown in figure 77 below. t ji = (90.8 mw)(60c/w + 50c/w) + 100c = 110c t jo = (217.3 mw)(30c/w + 50c/w) + 100c = 117c both of which are within the absolute maximum specifi- cation of 125c. if we, however, assume a worst case pcb layout and no air flow where the estimated q 4a and q 9,10a are 100c/w. then the junction temperatures become t ji = (90.8 mw)(60c/w + 100c/w) + 100c = 115c t jo = (217.3 mw)(30c/w + 100c/w) + 100c = 128c the output ic junction temperature exceeds the abso- lute maximum specification of 125c. in this case, pcb layout and airflow will need to be designed so that the junction temperature of the output ic does not exceed 125c. if the calculated junction temperatures for the thermal model in figure 78 is higher than 125c, the pin temper- ature for pins 9 and 10 should be measured (at the pack- age edge) under worst case operating environment for a more accurate estimate of the junction temperatures. t p4 t p9,10 4a = 50c/w* 9,10a = 50c/w* t a i4 = 60c/w o9,10 = 30c/w t ji t jo
32 printed circuit board layout considerations adequate spacing should always be maintained be- tween the high voltage isolated circuitry and any input referenced circuitry. care must be taken to provide the same minimum spacing between two adjacent high-side isolated regions of the printed circuit board. insufficient spacing will reduce the effective isolation and increase parasitic coupling that will degrade cmr performance. the placement and routing of supply bypass capacitors requires special attention. during switch ing transients, the majority of the gate charge is supplied by the bypass capacitors. maintaining short bypass capacitor trace lengths will ensure low supply ripple and clean switch- ing waveforms. ground plane connections are necessary for pin 4 (gnd1) and pins 9 and 10 (v ee ) in order to achieve maximum power dissipation as the hcpl-316j is designed to dissi- pate the majority of heat generated through these pins. actual power dissipation will depend on the application environment (pcb layout, air flow, part placement, etc.) see the thermal model section for details on how to es- timate junction temperature. the layout examples below have good supply bypassing and thermal properties, exhibit small pcb footprints, and have easily connected signal and supply lines. the four examples cover single sided and double sided compo- nent placement, as well as minimal and improved per- formance circuits. figure 79. recommended layout(s).
for product in f ormation and a complete list o f distributors, please go to our website: www.avagotech.com avago, avago technologies, and the a logo are trademarks o f avago technologies in the united states and other countries. data subject to change. cop y right ? 2005 - 2011 avago technologies. all rights reserved. obsoletes av01 - 0579en av02 - 0717en - march 28, 2011 figure 80. minimum led skew for zero dead time. figure 81. waveforms for dead time calculation. system considerations propagation delay difference (pdd) the hcpl-316j includes a propagation delay difference (pdd) specification intended to help designers minimize dead time in their power inverter designs. dead time is the time period during which both the high and low side power transistors (q1 and q2 in figure 62) are off. any overlap in q1 and q2 conduction will result in large currents flowing through the power devices between the high and low voltage motor rails, a potentially cata- strophic condi tion that must be prevented. to minimize dead time in a given design, the turn-on of the hcpl-316j driving q2 should be delayed (relative to the turn-off of the hcpl-316j driving q1) so that under worst-case conditions, transistor q1 has just turned off when transistor q2 turns on, as shown in figure 80. the amount of delay necessary to achieve this condition is equal to the maxi mum value of the propagation delay difference specification, pdd max , which is specified to be 400 ns over the operating temperature range of -40c to 100c. delaying the hcpl-316j turn-on signals by the maximum propaga tion delay difference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. the maximum dead time is equivalent to the difference between the maximum and minimum propagation delay difference specifications as shown in figure 81. the maximum dead time for the hcpl-316j is 800 ns (= 400 ns - (-400 ns)) over an operat- ing temperature range of -40c to 100c. note that the propagation delays used to calculate pdd and dead time are taken at equal tempera tures and test conditions since the optocouplers under consider a tion are typically mounted in close proximity to each other and are switching identical igbts. t phl max t plh min pdd* max = (t phl - t plh ) max = t phl max - t plh min *pdd = propagation delay note: for pdd calculations the propagation delays are taken at the same temperature and test conditions. v out1 v in+2 v out2 v in+1 q1 on q2 off q1 off q2 on t plh min maximum dead time (due to optocoupler) = (t phl max - t phl min ) + (t plh max - t plh min ) = (t phl max - t plh min ) C (t phl min - t plh max ) = pdd* max C pdd* min *pdd = propagation delay difference note: for dead time and pdd calculations all propagation delays are taken at the same temperature and test conditions. v out1 v in+2 v out2 v in+1 q1 on q2 off q1 off q2 on t phl min t phl max t plh max = pdd* max (t phl- t plh ) max

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